View AGB75LC04-QU-E_4989478.PDF datasheet online --- IC-ON-LINE

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Highly Integrated Amulet Graphical OS Chip TM for Color Graphical User Interfaces Introduction: Amulet's new GUI processor for color displays enables OEMs and design firms to take their products to the next level by implementing interactive color-rich GUIs designed in dynamic HTML. The Graphical OS Chip TM includes all of the hardware and software required to turn a color LCD and touch panel into a user interface. Amulet's solution is perfect for many embedded system applications, including appliances, consumer electronics, industrial controls, medical equipment and office automation. The accelerated graphic memory architecture allows for concurrent access to 3 individual memory subsystems for simultaneous program execution, LCD refresh, and frame buffer rendering. Features: * Integrated LCD Controller Supports Passive and Active displays up to 24 bits per pixel * USB 2.0, TWI, UART, and SPI Interfaces * Power Management Controller for Low Power Operation * Directly Connects to 4- and 5-wire Resistive Touch Panels * Up to 45 General Purpose IO Lines in BGA * Drag-and-drop GUI Creation in Dynamic HTML * PNG, GIF, and JPEG Image, and GIF Animation Support * Built-in Royalty-free Graphical Operating System * Inexpensive Development Tools * PC Based UI Simulator Available to SimplifyUI Prototyping * Built-in copy protection option to protect unauthorized duplication of user's product
COLOR CHIP FAMILY
AGB75LC04-QU-E AGB75LC04-BG-E
Data Sheet
Datasheet 2.2 - 0609
AGB75LC04
2
Typical Application Circuit
Cloak Crystal (12 MHz) 3.3V and 1.2V Power Supply Amulet Color Chip Reset SDRAM*
Dataflash*
* Typical Serial Flash: Atmel AT45DB321D * Typical SDRAM: ISSI IS42S32200E-6TL
3
3.1
Package and Pinout
208-pin PQFP Package (Top View)
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AGB75LC04
Datasheet 2.2 - 0609 3.11 Device and 208-pin PQFP Package Maximum Weight
AGB75LC04
5670.1
3.12 208-pin PQFP Package Characteristics
mg
Moisture Sensitivity Level
3.13 Package Reference
3
JEDEC Drawing Reference JESD97 Classification
MS-029 e3
3.2
225-pin BGA Package
X
0.12
Z
A1 BALL PAD CORNER
0.10
4X
0.10 A
Z
Z
D
Y
&b
& 0.15 M & 0.08 M
ZXY Z
E
Seating Plane A2
Top View
Side View
A1 BALL PAD CORNER
e
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Common Dimensions
(Unit of Measure = mm)
A B C D E F G H J K L M N P R
Symbol D E A A1 A2 e b
MIN
NOM 13.00 BSC 13.00 BSC
MAX
NOTE
_ 0.25 0.85
_ _ _ 0.80 BSC
1.70 _ _
3 3
0.90 REF
0.90 REF
e
(225 Solder Balls)
Bottom View
0.45
0.50
0.55
4
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Datasheet 2.2 - 0609 3.21 Device and 225-ball LFBGA Package Maximum Weight
AGB75LC04
365.2
3.22 225-ball LFBGA Package Characteristics
mg
Moisture Sensitivity Level
3.23 Package Reference
3
JEDEC Drawing Reference JESD97 Classification
3.24 Soldering Information
MO-205 e1
Note: 1 The top package body size may be smaller than the bottom package size by as much as 0.15 mm 2 Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3 Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm.
Ball Land Soldering Mask Opening
0.530 mm +/- 0.03 0.370 mm to 0.03 mm
3.3
Pin Descriptions Type Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Input Output Input Output Input I/O I/O Output Output Output Type Output Output Output Description Supply Voltage 3.3V A2D VCC 3.3V PLLA 3.3V Core Voltage 1.2V VDD MAIN OSC 1.2V VDD OSC32 1.2V Backup I/O Line Power 1.2V Must be connected PLLB 1.2V VDD OSC 1.2V Separate path to ground for Main Oscillator Separate path to ground for Oscillator Separate path to ground for Backup Separate path to ground for ADC Analog Separate path to ground for PLLB Separate path to ground for PLLA See External Circuit Diagrams Main Oscillator Input 12MHz Main Oscillator Output PLLA Filter Driven to 0. Do not drive over 1.2V 0 to1.2V Reset Active Low Data Bus Address Bus SDRAM makes data output go Hi-Z / blocks data input SDRAM makes data output go Hi-Z / blocks data input Description BS0 - SDRAM Bank Select BS1 - SDRAM Bank Select System Clock Active on positive going edge to sample all inputs
Pin Name Power Supplies VCC 3.3V AVCC VDDPLLA VCORE 1.2V VDDOSC VDDOSC32 Backup VCC VDDPLLB VDDOSC GND GNDOSC GNDOSC32 GNDBU AGND GNDPLLB GNDPLLA Clocks, Osillators and PLL Main OSC XIN Main OSC XOUT PLLA Filter Input Shutdown, Wake-up Logic Shut Down Control Wake-up Control Reset /Reset External Bus Interface DATA0 - DATA31 ADDR0 - ADDR12 SDRAM DQM0 DQM2 Pin Name SDRAM BSO SDRAM BS1 SDRAM CLK
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AGB75LC04
SDRAM CLK EN SDRAM WR SDRAM RAS SDRAM CAS SDRAM ADDR10 SDCS A2D/GPIO A2D Ref Touch YTouch XTouch Y+ Touch X+ A2D LCD Signals Pixel Data 0 - 23 Pixel Clock / DCLK Frame Clock
Active High Clock Enable freezes clock from the next operation Active Low Enables Write operation and Row Output precharges Output Active Low Row Address Strobe Output Active Low Column Address Strobe Output Row and Column addresses Output SDRAM Controller chip select See External Circuit Diagrams An. Input Connect to Analog 3.3V An. Input Touch panel YAn. Input Touch panel XAn. Input Touch panel Y+ An. Input Touch panel X+ An. Input A2D or GPIO Output Output Output Output LCD Pixel Data LCD Drive Signal. LCD crystal polarization clock. Clock Pulse. Users can specify the whether to clock on rising or falling edge. Hsync Signal . This output goes active for one clock period after all the serial data for the current line has been shifted to the TFT LCD. Line Pulse Signal. This output goes active after all the serial data for the current line has been shifted to the STN LCD Vsync Signal. TFT LCD First frame synchronization. Frame Out Signal. STN LCD first frame synchronization Display Control Signal. LCD power ( 1 = ON, 0 = OFF ) Output Enable System Power Up Mode ( 1 = Program, 0 = Normal ) See External Circuit Diagrams Description SPI Clock SPI Data In SPI Data Out
Hsync
Output
LP Vsync FO DISP OE Program Mode SPI Pin Name SPI SCLK SPI MISO SPI MOSI
Output Output Output Output Output Input Type Output Input Output
SPI CS1 SPI CS2 SPI CS3 SPI Flash CS TWI SDA SCL UARTs CommU TXD CommU RXD ProgU TXD ProgURXD UART2 TXD UART2 RXD UART2_SCK UART2 RTS UART2 CTS USB USB DDM USB DDP VBUS GPIO GPIOn Programmable Timers PWM0 PWM1 PWM2 Reserved RSVD N/C
Output Output Output I/O I/O I/O Output Input Output Input Output Input Output Output Input Analog Analog Input I/O Output Output Output
SPI Chip Select SPI Chip Select SPI Chip Select SPI Data Flash Chip Select Serial Data Serial Clock Asynchronous Serial-Data Output Asynchronous Serial-Data Input Asynchronous Serial-Data Output Asynchronous Serial-Data Input Asynchronous Serial-Data Output Asynchronous Serial-Data Input Serial Clock Request To Send Clear To Send See External Circuit Diagrams USB Device Port Data USB Device Port Data+ Vbus Monitor for host detection Has a 100K programmable pull-up Programmable Clock 0 Programmable Clock 1 Programmable Clock 2 Reserved Test Pins No Connection
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3.4
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
208-pin PQPF Package Pinout
Name VCC 3.3V + pullup VCC 3.3V + pullup DATA31 N/C DATA30 VCC 3.3V + pullup DATA29 RSVD DATA28 GND DATA27 VCC 3.3V DATA26 Reset DATA25 N/C DATA24 CommU RXD Pixel Data 8 CommU TXD Pixel Data 9 VCORE 1.2V Pixel Data 10 GND Pixel Data 11 Program Mode TPCal ADDR6 ADDR7 VCC 3.3V ADDR8 ADDR9 N/C ADDR11 ADDR12 VCORE 1.2V GND GND SDRAM CAS N/C SDRAM RAS SDRAM BS 0 ADDR10 VCC 3.3V SDRAM BS1 Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 Name LP / Hsync FO / Vsync VCC 3.3V GND DISP TWI SDA* TWI SCLK* N/C PWM0 PWM1 FC / OE N/C GND GND PWM2 VCC 3.3V Pixel Data 12 Pixel Data 0 Pixel Data 13 Pixel Data 1 Pixel Data 14 Pixel Data 2 Pixel Data 15 VCORE 1.2V VCC 3.3V Pixel Data 3 GND Pixel Data 4 Pixel Data 5 Pixel Data 6 Pixel Data 7 VBUS SDRAM DQM3 ProgU TXD Pixel Data 16 GND Pixel Data 17 ProgU RXD Pixel Data 18 SPI MISO Pixel Data 19 VCC 3.3V N/C VCORE 1.2V GPIO2* Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 Name ADDR5 GND VCC 3.3V ADDR4 ADDR3 VCORE 1.2V UART2 RXD ADDR2 UART2 TXD GND N/C ADDR1 SDRAM CLK EN ADDR0 SDRAM WE VCC 3.3V SDRAM CLK SDRAM DQM2 Pixel Data 20 GND SDRAM DQM0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 GND DATA6 VCC 3.3V DATA5 Pixel Data 21 GND Pixel Data 22 Pixel Data 23 UART2 SCK VCORE 1.2V UART2 RTS GND UART2 CTS USB DDM USB DDP Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 Name VDDOSC32 GND N/C GNDOSC32 BackUp VCC Shut Down Control Wake-Up Control N/C RSVD GNDBU A2D Ref Touch YTouch XTouch Y+ Touch X+ A2D4 / GPIO4* AVCC 3.3V AGND GND DATA23 VCC 3.3V DATA22 GND DATA21 SDRAM CS DATA20 VCORE 1.2V DATA19 DATA18 DATA17 DATA16 N/C N/C SPI CS3 SPI CS2 SPI CS1 GND VCORE 1.2V GND SDRAM DQM1 N/C VCC 3.3V VDDPLLB GNDPLLB GNDOSC
Pin 46 47 48 49 50 51 52
Name N/C N/C N/C N/C GND N/C Pixel Clock
Pin 98 99 100 101 102 103 104
Name SPI MOSI SPI SCLK GND SPI Flash CS N/C N/C VCC 3.3V
Pin 150 151 152 153 154 155 156
Name GPIO3* VCC 3.3V DATA4 DATA3 DATA2 DATA1 DATA0
Pin 202 203 204 205 206 207 208
Name Main OSC XIN Main OSC XOUT VDDOSC VDDPLLA GNDPLLA PLLA Filter Input GNDPLLA
*NOTE: Multi-function Pin. See Multiplex I/O Section for more information. 3.5
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4
225-pin BGA Package Pinout
Name GPIO4 SPI SCLK SPI MOSI N/C Pixel Data 17 VBUS Pixel Data 5 Pixel Data 15 Pixel Data 12 N/C N/C GPIO12 DISP GPIO36 N/C ADDR4 GPIO15 GPIO14 GPIO2 ProgU TXD Pixel Data 16 Pixel Data 7 Pixel Data 3 Pixel Data 14 PWM2 PWM0 TWI SDA GPIO9 GPIO34 N/C GPIO18 N/C GPIO16 GPIO39 Pin D13 D14 D15 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 G1 Name LP / Hsync GPIO35 GPIO6 ADDR1 ADDR2 GPIO40* UART2 TXD VCC 3.3V SPI Flash CS N/C Pixel Data 1 Pixel Data 0 TWI SCLK GPIO11 Pixel Clock GPIO7 N/C ADDR10 SDRAM WE ADDR0 UART2 RXD SDRAM CLK EN GPIO19 SDRAM DQM0 VCC 3.3V Pixel Data 18 VCC 3.3V N/C GPIO8 GPIO5 ADDR12 SDRAM BS0 N/C Pixel Data 20 Pin H10 H11 H12 H13 H14 H15 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 Name VCORE 1.2V DATA5 TPCal Program Mode ADDR7 ADDR8 DATA7 DATA6 Pixel Data 23 DATA3 USB DDP DATA2 GND GND GND N/C Pixel Data 9 CommU RXD CommU TXD Pixel Data 11 ADDR6 Pixel Data 21 Pixel Data 22 GPIO3 UART2 CTS GPIO22 Wake-Up Control VCC 3.3V VCORE 1.2V VCC 3.3V Main OSC XOUT DATA25 VCC 3.3V + pullup DATA24 Pin M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Name DATA22 A2D7 / GPIO44* N/C GPIO30 GNDPLLA N/C VCC 3.3V + pullup DATA28 N/C GPIO21 GPIO24 Backup VCC N/C Touch X+ AVCC 3.3V DATA20 SPI CS3 GPIO27 N/C PLLA Filter Input Main OSC XIN VDDPLLA DATA29 Reset DATA4 DATA3 Shut Down Control RSVD Touch YA2D5 / GPIO42 DATA21 DATA16 SPI CS1 GPIO28
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Pin C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 Name SPI MISO Pixel Data 19 ProgU RXD Pixel Data 4 Pixel Data 13 FC/ OE GPIO10 GPIO38 N/C N/C SDRAM BS 1 GPIO20 ADDR3 ADDR5 N/C GPIO17 GPIO13 SDRAM DQM3 Pixel Data 6 Pixel Data 2 PWM1 GPIO37 FO / Vsync Pin G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 H1 H2 H3 H4 H5 H6 H7 H8 H9 Name SDRAM CLK SDRAM DQM2 DATA14 DATA15 VCORE 1.2V GND GND GND VCC 3.3V SDRAM RAS N/C* ADDR9 SDRAM CAS ADDR11 DATA10 DATA9 DATA13 DATA11 DATA12 VCC 3.3V GND GND GND Pin K14 K15 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 Name Pixel Data 8 Pixel Data 10 UART2 SCK UART2 RTS DATA1 GPIO25 VDDOSC32 GNDBU A2D4 / GPIO4* SDRAM CS DATA17 GNDPLLB DATA31 VCC 3.3V + pullup GPIO33 DATA30 DATA18 USM DDM Pin P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Name GNDOSC SDRAM DQM1 VDDOSC RSVD DATA27 N/C A2D Ref Touch Y+ A2D6 / GPIO43* AGND DATA23 DATA19 N/C SPI CS2 GPIO26 GPIO29 GPIO31 GPIO32 VDDPLLB DATA26
AGB75LC04
GPIO23 DATA0 GND GNDOSC32 Touch X-
*NOTE: Multi-function Pin. See Multiplex I/O Section for more information. 3.6 Multiplex I/O
The pins shown in the following tables have multiple function per pin. The tables describe the peripheral function, general purpose input and general purpose output. 4 Function Pins: Pin 58 / B12 59 / E10 3 Function Pins: Pin 208 PQFP 172 225 BGA N5 L7 P6 R4 M8 Function A TWI_SDA TWI_SCLK Function B UART2 RXD UART2 TXD General Purpose Input Yes (GPIO0) Yes (GPIO1) General Purpose Output Yes (GPIO0) Yes (GPIO1) General Purpose Yes (GPIO4) Yes (GPIO3) Yes (GPIO4) Yes (GPIO42) Yes (GPIO43) Yes (GPIO44)
Function A A2D (A2D4) A2D (A2D3) A2D (A2D4) A2D (A2D5) A2D (A2D6) A2D (A2D7)
General Purpose Input Yes (GPIO4) Yes (GPIO3) Yes (GPIO4) Yes (GPIO42) Yes (GPIO43) Yes (GPIO 44)
2 Function Pins: Pin 208 PQFP 97 150 225 BGA B4 K3 F12 D15 E13 F11 B13 C11 E11 A12 D6 B3 B2 C3 D5 C1 F5 D1 N1 K5 M2 N2 L4 R10 N9 P10 R11 M10 R12 R13 L13 B14 D14 A14 D11 C12 C4 E3 A1
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General Purpose Input Yes (GPIO2) Yes (GPIO3) Yes (GPIO2) Yes (GPIO3) Yes (GPIO5) Yes (GPIO6) Yes (GPIO7) Yes (GPIO8) Yes (GPIO9) Yes (GPIO10) Yes (GPIO11) Yes (GPIO12) Yes (GPIO13) Yes (GPIO14) Yes (GPIO15) Yes (GPIO16) Yes (GPIO17) Yes (GPIO18) Yes (GPIO19) Yes (GPIO20) Yes (GPIO21) Yes (GPIO22) Yes (GPIO23) Yes (GPIO24) Yes (GPIO25) Yes (GPIO26) Yes (GPIO27) Yes (GPIO28) Yes (GPIO29) Yes (GPIO30) Yes (GPIO31) Yes (GPIO32) Yes (GPIO33) Yes (GPIO34) Yes (GPIO35) Yes (GPIO36) Yes (GPIO37) Yes (GPIO38) Yes (GPIO39) Yes (GPIO40) Yes (GPIO41)
General Purpose Output Yes (GPIO2) Yes (GPIO3) Yes (GPIO2) Yes (GPIO3) Yes (GPIO5) Yes (GPIO6) Yes (GPIO7) Yes (GPIO8) Yes (GPIO9) Yes (GPIO10) Yes (GPIO11) Yes (GPIO12) Yes (GPIO13) Yes (GPIO14) Yes (GPIO15) Yes (GPIO16) Yes (GPIO17) Yes (GPIO18) Yes (GPIO19) Yes (GPIO20) Yes (GPIO21) Yes (GPIO22) Yes (GPIO23) Yes (GPIO24) Yes (GPIO25) Yes (GPIO26) Yes (GPIO27) Yes (GPIO28) Yes (GPIO29) Yes (GPIO30) Yes (GPIO31) Yes (GPIO32) Yes (GPIO33) Yes (GPIO34) Yes (GPIO35) Yes (GPIO36) Yes (GPIO37) Yes (GPIO38) Yes (GPIO39) Yes (GPIO40) Yes (GPIO41)
AGB75LC04
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AGB75LC04
4
Block Diagram
ARM7TDMI
ADDR0 - ADDR12
Amulet OS Fast SRAM 160K
Main OSC XIN Main OSC XOUT Program Mode T CAL V Core /RESET
DATA0 - DATA31 SDRAM CLK SDRAM CLK EN SDRAM WE SDRAM RAS SDRAM CAS SDRAM CS DQM0 - DQM3
SDRAM Controller
System Controller
Multi- Layer AHB Matrix
BS0, BS1
Pixel Data 0-7 (Red) Pixel Data 8-15 (Green)
SPI SCLK SPI CS0 - CS3 MISO MOSI
LCD Interface SPI
Pixel Data 16-23 (Blue) Pixel CLK V Sync / FO H Sync / LP OE / FC DISP
Prog U TXD Prog U RXD
Programming UART Communication UART USB
Peripheral Bridge
Touch Panel A2D TWI GPIO UART 2
TP A2D Ref A2D Touch 0 - 4
Comm U TXD Comm U RXD USB DDM USB DDP
Peripheral DMA Controller
SCL SDA
GPIO UAR T2 TXD UAR T2 RXD UAR T2 RTS UAR T2 CTS UAR T2 SCK
5
5.1
5.11
Connection Diagrams
LCD Connections
TFT LCD Connection
Amulet Pixel Data 0-7 Pixel Data 8-15 Pixel Data 16-23 VSYNC HSYNC Pixel Clock DISP DE
24 BIT
TFT LCD* R0-7 G0-7 B0-7 VSYNC HSYNC Pixel Clock DISP DE
Amulet Pixel Data 2-7 Pixel Data 10-15 Pixel Data 18-23 VSYNC HSYNC Pixel Clock DISP DE
18 BIT
TFT LCD* R0-5 G0-5 B0-5 VSYNC HSYNC Pixel Clock DISP DE
*Note: These diagrams assume LSB is always 0. Some displays may vary
5.12 TFT UPS052 LCD Connection
Amulet Amulet Pixel Data 0-7 Pixel Data 0-7 Pixel Data 8-15 Pixel Data 8-15 Pixel Data 16-23 Pixel Data 16-23 VSYNC VSYNC HSYNC HSYNC Pixel Clock Pixel Clock DISP DISP DE DE
TFT LCD* TFT LCD* Data 0-7 Data 0-7
VSYNC VSYNC HSYNC HSYNC Pixel Clock Pixel Clock DISP DISP DEDE
*Note: These diagrams assume LSB is always 0. Some displays may vary
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5.13
STN LCD Connection
Amulet Amulet PixelPixel Data 0-7 Data 0-7 Pixel Data 8-15 Pixel Data 8-15 Pixel Data 16-23 Pixel Data 16-23 VSYNC VSYNC HSYNC HSYNC Pixel Clock Pixel Clock DISP DISP DE DE
STN LCD* STN LCD* Data Data 0-7 0-7
Frame Frame Out Out Line Line Pulse Pulse Pixel Clock Pixel Clock DISP DISPFrame Clock Frame Clock
*Note: These diagrams assume LSB is always 0. Some displays may vary 5.2 Flash Connection Amulet Amulet SPI Flash CS SPI Flash CS SPI MOSI SPI MOSI SPI SCLK SPI SCLK SPI MISO SPI MISO Flash Flash Chip Select Chip Select Serial Input Serial Input Serial Clock Serial Clock Serial Output Serial Output
5.3
5.31
SDRAM Connection
32-bit Data SDRAM
Amulet Data0 - Data31 SDRAM DQM0 - DQM3 ADDR0 - ADDR10 SDRAM BS0 - BS1 SDRAM CAS SDRAM RAS SDRAM WE SDRAM CS SDRAM CLK EN SDRAM CLK
32 BIT
SDRAM Data0 - Data31 DQM0 - DQM3 ADDR0 - ADDR10 Bank Address 0 -1 CAS RAS WE Chip Select Clock Enable Clock
6
6.1
Pixel Data Connections for color depth support
TFT LCD Connection Table, 1 clock per pixel Pixel Data Connection
Amulet
0 R0 1 R1 2 R2 3 R3 R1 4 R4 R2 R1 R1 5 R5 R3 R2 R2 6 R6 R4 R3 R3 7 R7 8 9 10 11 12 13 14 15 16 B0 17 B1 18 B2 19 B3 B1 20 B4 B2 B1 B1 21 B5 B3 B2 B2 22 B6 B4 B3 B3 23 B7 B5 B4 B4
LCD Bit Depth
24 18 16 15
G0 G1 G2 G3 G4 G5 G6 G7
N/C N/C R0
R5 N/C N/C G0 G1 G2 G3 G4 G5 N/C N/C B0
N/C N/C N/C R0 N/C N/C N/C R0
R4 N/C N/C G0 G1 G2 G3 G4 G5 N/C N/C N/C B0 R4 N/C N/C N/C G0 G1 G2 G3 G4 N/C N/C N/C B0
Note: Amulet Pins 0, 8, and 16 are the least significant bits of the Red, Green, and Blue pixel data, respectively
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6.2
TFT UPS052 LCD Connection Table Pixel Data Connection
Amulet
24 18 15 0 0 1 1 2 2 0 3 3 1 0 4 4 2 1 5 5 3 2 6 6 4 3 7 7 5 4
LCD Bit Depth
N/C N/C
N/C N/C N/C
6.3
STN LCD Connection Table Pixel Data Connection
Amulet
8 4 0 0 0 1 1 1 2 2 2 3 3 3 4 4 5 5 6 6 7 7
LCD Bit Depth
N/C N/C N/C N/C
7
7.1
External Circuit Diagrams
Touch Panel Filter+
Touch Panel 4 3 2 1 Touch X+ Touch Y+ Touch XTouch Y-
0.01uF
0.01uF
0.01uF
0.01uF
Touch Pane l Filter
7.2
Serial Data Flash
SPI MOSI SPI SCLK RE SET SPI CS 2 3 4
SI SCK /RES ET /CS
SO GND VCC /WP
8 7 6 5
SPI MISO
3.3V
0.1uF
7.3
USB DDM USB DD P
USB Interface
2 27 ohm 3 27 ohm 4 1 27 Kohm 47 Kohm VBUS
330 Kohm
330 Kohm
7.4
Main OSC Interface
Main O SC XIN Main O SC XOU T
1Kohm
12 M H z 33pF 33pF
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7.5
PLLA Filter
PLL A Filter Input
1nF 300 ohm
0.1uF
7.6
Reset Circuit
Rese t Pin 14
Rese t 3.3V 3.3V GND
Swi tch
0.1uF
7.7
Mandatory Pullups
Vcc (Pin 1 )
100kohm
3.3V
Vcc (Pin 2)
100kohm
3.3V 3.3V
Vcc (Pin 6)
100kohm
Wak e Up Control
100kohm
1.2V
8
8.1
Environmental,ElectricalandPowerSpecifications
AGB75LC04-XX-X: 208 pin: AGB75LC04-QU-E / 225 pin: AGB75LC04-BG-E Recommended Operating Conditions 3.0V to 3.6V, 3.3V nominal 1.08V to 1.32V, 1.2V nominal
Power supply Vcc Power supply Vcore 8.2
Environmental Specifications -40 to +85C - 60C to +150C
Operating temperature Storage temperature 8.3
DC Characteristics 22mA @ 1.2V TBD -0.3V to 0.8V 2V to (VCC + 0.3V) 70 kOhm to 175 kOhm, 100 kOhm nominal 8mA Vcore = 1.2V, excluding Power on Reset All inputs driven, NRST=1 Vcore = 1.2V, logic cells consumption, including Power on Reset All inputs driven, WKUP=0 T = 25oC 600uA
Vcore Supply current VDDIO Supply current VL Input Low Level Voltage VH Input High Level Voltage Rpullup Pull Up Resistance IO Output Current
ISC Static Current
T = 25oC
30uA
*The DC characteristics above are applicable to the operating temperature range: TA = -40oC to 85oC, unless otherwise specified and are certified for a junction temperature up to TJ = 100oC. The values are estimated values with operating conditions as follows: * VDDIO = VDDPLLA = VAVDD = 3.3V * VDDCORE = VDDBU = VDDOSC = VDDOSC32 = 1.2V * TA = 25oC * There is no consumption on the I/Os of the device
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8.4
SDRAM
8.41 Capacitance Load on Data, Control and Address Lines 3.3V 50pF 1.8V 30pF 8.42 3.3V 1.8V Capacitance Load on SDCK Pad 10pF 10pF
8.5
RoHS compliant Package Options
208-PQFP 28x28x3.4mm, 0.5 mm pin pitch 225-ball LFBGA 13x13x1.4mm, 0.8 mm ball pitch 8.6 Power Consumption
The advanced power management controller has a very slow clock operating mode and software programmable power optimization capabilities. Along with a reset controller and shutdown controller, this gives the AGB75LC04-XX-X several low-power options. .
9
TimingSpecifications
9.1 LCD The following tables and figures show basic information on interfacing with the LCD controller. For more detailed information on how to configure the LCD controller, please refer to the HTML Compiler Help files.
9.11 TFT
Item Hsync Pulse Width Hsync Back Porch Hsync Period Hsync Display Data Hsync Front Porch Vsync Pulse Width Vsync Back Porch Vsync Period Vsync Display Data Vsync Front Porch
Symbol Thpw Thbp Thp Thd Thfp Tvpw Tvbp Tvp Tvd Tvfp
Unit Pixel Clock Pixel Clock Pixel Clock Pixel Clock Pixel Clock Hsync Hsync Hsync Hsync Hsync
Pixel Clock Hsync Thpw Thp Thbp Data Thd Output Enable Hsync Vsync Tvpw Tvp Tvbp Lines of Data Tvd Tvfp Thfp
Item Pixel Data Setup Time Hold Time
Typical 0.75 * Pixel Clock Period 0.25 * Pixel Clock Period
Unit ns ns
9.12
STN
Item Line Pulse Width Line Pulse Porch Frame Frequency
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Symbol Thpw Thbp Thp
Unit System Clock System Clock 80MHz Clock
AGB75LC04
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Pixel Clock Data Line Pulse Frame Out Frame Clock
9.121 STN Monochrome and Grayscale
Item Setup Time Pixel Data Hold Time
9.122 STN Color
Typical 0.75 * Pixel Clock Period 0.25 * Pixel Clock Period
Unit ns ns
Item Setup Time Pixel Data Hold Time 9.2 SPI Item Setup Time before SPI SCLK rises Hold Time after SPI SCLK rises Setup Time before SPI SCLK falls Hold Time after SPI SCLK falls
Typical 0.5 * Pixel Clock Period 0.5 * Pixel Clock Period
Unit ns ns
Min 3.66 0 3.52 0
Max
Unit ns ns ns ns
MISO
SPI SCLK rising to MOSI Valid SPI SCLK rising to MOSI change SPI SCLK falling to MOSI Valid SPI SCLK falling to MOSI change -0.67 -0.81
-0.6
ns ns
-0.19
ns ns
NOTE: Load Capacitance is 8pF for MISO and 6pF for SPI SCLK and MOSI 9.3 TWI Item Setup Time Serial Data Hold Time 9.4 SDRAM Typical TBD TBD Unit ns ns
SDRAM CLK Control/Address tCA DO setu p Data In tD Isetu p tD Iho ld
tCA DO ho ld
Data Out tCA DO setu p Item Symbol tCADOsetup tCADOhold tDIsetup tDIhold tCA DO ho ld Typical 5.51 5.95 0.6 0.62 Unit ns ns ns ns
Setup Control/Address/Data Time Out1 Hold Time Setup Time Data Input Hold Time
Datasheet 2.2 - 0609
AGB75LC04
Datasheet 2.2 - 0609 9.41 SDRAM PC100 Characteristics (3.3V Supply, CL=2)
AGB75LC04
Unit
MHz ns
Item
SDRAM Frequency Control/Address/Data in Setup Control/Address/Data in Hold1 Data Out Access Time after SDRAM CLK rising Data Out Change Time after SDRAM CLK rising 9.42
1
Min
2 1
Max
100
6 3
ns ns
SDRAM PC133 Characteristics (3.3V Supply, CL=3)
Item
SDRAM Frequency Control/Address/Data in Setup Control/Address/Data in Hold Data Out Access Time after SDRAM CLK rising Data Out Change Time after SDRAM CLK rising
1 1
Min
1.5 0.8
Max
133
Unit
MHz ns
5.4 3.0
ns ns
9.5
USB
Item Transition Rise Time Transition Fall Time2 Rise/Fall Time Matching2
2
Min 4 4 90
Max 20 20 111.11
Unit ns ns %
NOTE: 1. Control/Address is the set of the following timings: ADDR0-ADDR12, SDRAM10, SDRAM CAS, SDRAM RAS, SDRAM CLK, SDRAM CLK EN, BSx, DOMx and SDRAM WE. 2. In Full Speed wit Load Capacitance of 50pF.
10
Display Data Pattern
SEG 1 D0 ROW #1 D1 D2 D3 D0 D1
SEG 320 D2 D3
ROW #240
D0
D1
D2
D3
D0
D1
D2
D3
11
System Parameters
LCDs supported Interfaces supported Number of GPIO Integrated Touch panel Decoder SDRAM Flash
Up to 800xRGBx600 resolution. Active and Passive display support USB, UART, TWI and SPI 39 pins on the LFBGA and up to 5 pins on the PQFP package 4- or 5-wire, calibration, noise filtering, gesture recognition 32-bit parallel interface 1Mbit to 512Mbit serial data flash
12
Revision History
Date Revision 2.0 2.1 Notes First complete datasheet Rename SDRAM Blank Select to BSx Added BGA Information Added Packaging Information.
12 February 2009 7 May 2009
Datasheet 2.2 - 0609
AGB75LC04
Datasheet 2.2 - 0609
AGB75LC04
13
Ordering Information
Ordering Code Package 208 PQFP 208 PQFP 225 BGA Package Type RoHS Compliant RoHS Compliant RoHS Compliant Temperature Operating Range -20oC to 60oC Industrial -40oC to 85oC Industrial -40oC to 85oC
STK-480272C AGB75LC04-QU-E AGB75LC04-BG-E
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